The invention relates to a method of manufacturing semiconductor substrates and an assembly thereof, in particular of silicon substrates, e.g., for SOI or MEMS, by bonding two semiconductor wafers (bonding) and thinning (for instance, splitting or separating) one of the two wafers, thereby providing the advantage of a reduced edge defect area, which is achieved by a specific “edge rounding” of the semiconductor wafers to be bonded. The bonded wafers are considered as a wafer composite in the sense of a “bonded wafer assembly”.
For the fabrication of semiconductor substrates including patterned and non-patterned buried levels, as for instance in the SOI or MEMS technology, typically two silicon wafers are connected to each other in a laminar manner (bonded). This technique was developed by Tong and Goesele and is referred to as Semiconductor Wafer Bonding, cf., Science and Technology of Semiconductor Wafer Bonding, Tong/Goesele, John Wiley and Sons, USA (1999), ISBN 0-471-57481-3, December 1998.
In this case on one or both wafer surfaces to be bonded are located in the layer to be buried or a system of layers, which may not be positioned at the surface due to the manufacturing process.
After bonding one of the two wafers is thinned, for instance, by grinding/etching/polishing, or separated parallel with respect to a predetermined break plane that is not located within the bonding plane, for example, in SOI layer transfer techniques. The remaining wafer including the layer structure is referred to as device wafer, while the thinned or separated wafer may be referred to as donator wafer and may be used, if required, for other purposes after separation.
EP-A 451 993 (Shin-Etsu) discloses a method for manufacturing a substrate for semiconductor devices. Two semiconductor wafers are connected to each other by “semiconductor wafer bonding”, wherein an edge geometry is provided on the wafers to be bonded, which allows as much as possible to provide a defect-free perimeter region and a large usable wafer surface after reducing the thickness of one of the wafers. In this method wafers of different diameters are used so that after the thinning a geometry according to FIG. 1 in this document is obtained relative to a geometry of the perimeter and edge region based on a technology referred to as prior art according to FIG. 3c in this document. Associated flattenings (referred to as “bevels” w8, w5) are indicated without reference to the wafer diameter are provided with scale factors such that the inner edge or the inner ends of both flattenings are radially located substantially equally, while the outer ends are intentionally not located in this manner, cf., column 6, lines 25 to 37. As a result, facets of different length and a protruding edge of the larger wafer are obtained after the thinning is performed.
If wafers of a standard edge geometry are used for the connection (bonding), a faulty or even a completely missing connection is caused (non-bonded regions). After the thinning or separation or splitting apart of the donator wafer the layer (stack) transferred from the donator wafer to the device wafer may delaminate in these regions.
Consequently, an edge region that is non-usable for the device fabrication and a non-defined edge geometry causing a negative technological affect, i.e., causing increased effort and preparation errors, are obtained.
One reason causing the non-bonded wafer edge region is the standard edge geometry of the wafer having a relatively long facet at the wafer surfaces to be bonded. In the vicinity of the facets a mechanical contact may not be established between the wafers to be bonded, which is a prerequisite for creating a bonding connection. The non-defined wafer edge area resulting therefrom after the thinning of the donator wafer caused difficulties in the further manufacturing process of the device wafer, e.g. issues with respect to resist coating and focussing (photolithography). The non-usable edge zone, which may typically reach up to 7 mm from the wafer edge into the interior of the wafer surface, also results in a significant loss of usable wafer surface. This loss may amount to about 9% for a 150 mm wafer.
It is the (technical) object of the present invention to provide a method for forming semiconductor substrates by bonding such that the non-usable edge region of the device wafer is reduced and the edge geometry is enhanced.